stm32l1xx_ll_sdmmc.c 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519
  1. /**
  2. ******************************************************************************
  3. * @file stm32l1xx_ll_sdmmc.c
  4. * @author MCD Application Team
  5. * @version V1.0.0
  6. * @date 5-September-2014
  7. * @brief SDMMC Low Layer HAL module driver.
  8. *
  9. * This file provides firmware functions to manage the following
  10. * functionalities of the SDMMC peripheral:
  11. * + Initialization/de-initialization functions
  12. * + I/O operation functions
  13. * + Peripheral Control functions
  14. * + Peripheral State functions
  15. *
  16. @verbatim
  17. ==============================================================================
  18. ##### SDMMC peripheral features #####
  19. ==============================================================================
  20. [..] The SD/SDIO MMC card host interface (SDIO) provides an interface between the APB2
  21. peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDIO cards and CE-ATA
  22. devices.
  23. [..] The MultiMedia Card system specifications are available through the MultiMedia Card
  24. Association website at www.mmca.org, published by the MMCA technical committee.
  25. SD memory card and SD I/O card system specifications are available through the SD card
  26. Association website at www.sdcard.org.
  27. CE-ATA system specifications are available through the CE-ATA work group web site at
  28. www.ce-ata.org.
  29. [..] The SDIO features include the following:
  30. (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
  31. for three different databus modes: 1-bit (default), 4-bit and 8-bit
  32. (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
  33. (+) Full compliance with SD Memory Card Specifications Version 2.0
  34. (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two
  35. different data bus modes: 1-bit (default) and 4-bit
  36. (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
  37. Rev1.1)
  38. (+) Data transfer up to 48 MHz for the 8 bit mode
  39. (+) Data and command output enable signals to control external bidirectional drivers.
  40. ##### How to use this driver #####
  41. ==============================================================================
  42. [..]
  43. This driver is a considered as a driver of service for external devices drivers
  44. that interfaces with the SDIO peripheral.
  45. According to the device used (SD card/ MMC card / SDIO card ...), a set of APIs
  46. is used in the device's driver to perform SDIO operations and functionalities.
  47. This driver is almost transparent for the final user, it is only used to implement other
  48. functionalities of the external device.
  49. [..]
  50. (+) The SDIO clock (SDIOCLK = 48 MHz) is coming from the PLL. Before start working with SDIO peripheral make sure that the
  51. PLL is well configured.
  52. The SDIO peripheral uses two clock signals:
  53. (++) SDIO adapter clock (SDIOCLK = 48 MHz)
  54. (++) APB2 bus clock (PCLK2)
  55. -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition:
  56. Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK))
  57. (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDIO
  58. peripheral.
  59. (+) Enable the Power ON State using the SDIO_PowerState_ON(hsdio)
  60. function and disable it using the function SDIO_PowerState_OFF(hsdio).
  61. (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros.
  62. (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT(hsdio, IT)
  63. and __SDIO_DISABLE_IT(hsdio, IT) if you need to use interrupt mode.
  64. (+) When using the DMA mode
  65. (++) Configure the DMA in the MSP layer of the external device
  66. (++) Active the needed channel Request
  67. (++) Enable the DMA using __SDIO_DMA_ENABLE() macro or Disable it using the macro
  68. __SDIO_DMA_DISABLE().
  69. (+) To control the CPSM (Command Path State Machine) and send
  70. commands to the card use the SDIO_SendCommand(),
  71. SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has
  72. to fill the command structure (pointer to SDIO_CmdInitTypeDef) according
  73. to the selected command to be sent.
  74. The parameters that should be filled are:
  75. (++) Command Argument
  76. (++) Command Index
  77. (++) Command Response type
  78. (++) Command Wait
  79. (++) CPSM Status (Enable or Disable).
  80. -@@- To check if the command is well received, read the SDIO_CMDRESP
  81. register using the SDIO_GetCommandResponse().
  82. The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the
  83. SDIO_GetResponse() function.
  84. (+) To control the DPSM (Data Path State Machine) and send/receive
  85. data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(),
  86. SDIO_ReadFIFO(), SDIO_WriteFIFO() and SDIO_GetFIFOCount() functions.
  87. *** Read Operations ***
  88. =======================
  89. [..]
  90. (#) First, user has to fill the data structure (pointer to
  91. SDIO_DataInitTypeDef) according to the selected data type to be received.
  92. The parameters that should be filled are:
  93. (++) Data TimeOut
  94. (++) Data Length
  95. (++) Data Block size
  96. (++) Data Transfer direction: should be from card (To SDIO)
  97. (++) Data Transfer mode
  98. (++) DPSM Status (Enable or Disable)
  99. (#) Configure the SDIO resources to receive the data from the card
  100. according to selected transfer mode.
  101. (#) Send the selected Read command.
  102. (#) Use the SDIO flags/interrupts to check the transfer status.
  103. *** Write Operations ***
  104. ========================
  105. [..]
  106. (#) First, user has to fill the data structure (pointer to
  107. SDIO_DataInitTypeDef) according to the selected data type to be received.
  108. The parameters that should be filled are:
  109. (++) Data TimeOut
  110. (++) Data Length
  111. (++) Data Block size
  112. (++) Data Transfer direction: should be to card (To CARD)
  113. (++) Data Transfer mode
  114. (++) DPSM Status (Enable or Disable)
  115. (#) Configure the SDIO resources to send the data to the card according to
  116. selected transfer mode.
  117. (#) Send the selected Write command.
  118. (#) Use the SDIO flags/interrupts to check the transfer status.
  119. @endverbatim
  120. ******************************************************************************
  121. * @attention
  122. *
  123. * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  124. *
  125. * Redistribution and use in source and binary forms, with or without modification,
  126. * are permitted provided that the following conditions are met:
  127. * 1. Redistributions of source code must retain the above copyright notice,
  128. * this list of conditions and the following disclaimer.
  129. * 2. Redistributions in binary form must reproduce the above copyright notice,
  130. * this list of conditions and the following disclaimer in the documentation
  131. * and/or other materials provided with the distribution.
  132. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  133. * may be used to endorse or promote products derived from this software
  134. * without specific prior written permission.
  135. *
  136. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  137. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  138. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  139. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  140. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  141. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  142. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  143. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  144. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  145. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  146. *
  147. ******************************************************************************
  148. */
  149. /* Includes ------------------------------------------------------------------*/
  150. #include "stm32l1xx_hal.h"
  151. /** @addtogroup STM32L1xx_HAL_Driver
  152. * @{
  153. */
  154. /** @defgroup SDMMC_LL SDMMC_LL
  155. * @brief Low layer module for SD and MMC driver
  156. * @{
  157. */
  158. #if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
  159. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
  160. /* Private typedef -----------------------------------------------------------*/
  161. /* Private define ------------------------------------------------------------*/
  162. /* Private macro -------------------------------------------------------------*/
  163. /* Private variables ---------------------------------------------------------*/
  164. /* Private function prototypes -----------------------------------------------*/
  165. /* Private functions ---------------------------------------------------------*/
  166. /** @defgroup SDMMC_LL_Exported_Functions SDMMC_LL Exported Functions
  167. * @{
  168. */
  169. /** @defgroup HAL_SDMMC_LL_Group1 Initialization/de-initialization functions
  170. * @brief Initialization and Configuration functions
  171. *
  172. @verbatim
  173. ===============================================================================
  174. ##### Initialization/de-initialization functions #####
  175. ===============================================================================
  176. [..] This section provides functions allowing to:
  177. @endverbatim
  178. * @{
  179. */
  180. /**
  181. * @brief Initializes the SDIO according to the specified
  182. * parameters in the SDIO_InitTypeDef and create the associated handle.
  183. * @param SDIOx: Pointer to SDIO register base
  184. * @param Init: SDIO initialization structure
  185. * @retval HAL status
  186. */
  187. HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
  188. {
  189. uint32_t tmpreg = 0;
  190. /* Check the parameters */
  191. assert_param(IS_SDIO_ALL_INSTANCE(SDIOx));
  192. assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge));
  193. assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass));
  194. assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave));
  195. assert_param(IS_SDIO_BUS_WIDE(Init.BusWide));
  196. assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
  197. assert_param(IS_SDIO_CLKDIV(Init.ClockDiv));
  198. /* Set SDIO configuration parameters */
  199. tmpreg |= (Init.ClockEdge |\
  200. Init.ClockBypass |\
  201. Init.ClockPowerSave |\
  202. Init.BusWide |\
  203. Init.HardwareFlowControl |\
  204. Init.ClockDiv
  205. );
  206. /* Write to SDIO CLKCR */
  207. MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
  208. return HAL_OK;
  209. }
  210. /**
  211. * @}
  212. */
  213. /** @defgroup HAL_SDMMC_LL_Group2 I/O operation functions
  214. * @brief Data transfers functions
  215. *
  216. @verbatim
  217. ===============================================================================
  218. ##### I/O operation functions #####
  219. ===============================================================================
  220. [..]
  221. This subsection provides a set of functions allowing to manage the SDIO data
  222. transfers.
  223. @endverbatim
  224. * @{
  225. */
  226. /**
  227. * @brief Read data (word) from Rx FIFO in blocking mode (polling)
  228. * @param SDIOx: Pointer to SDIO register base
  229. * @retval HAL status
  230. */
  231. uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)
  232. {
  233. /* Read data from Rx FIFO */
  234. return (SDIOx->FIFO);
  235. }
  236. /**
  237. * @brief Write data (word) to Tx FIFO in blocking mode (polling)
  238. * @param SDIOx: Pointer to SDIO register base
  239. * @param pWriteData: pointer to data to write
  240. * @retval HAL status
  241. */
  242. HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)
  243. {
  244. /* Write data to FIFO */
  245. SDIOx->FIFO = *pWriteData;
  246. return HAL_OK;
  247. }
  248. /**
  249. * @}
  250. */
  251. /** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
  252. * @brief management functions
  253. *
  254. @verbatim
  255. ===============================================================================
  256. ##### Peripheral Control functions #####
  257. ===============================================================================
  258. [..]
  259. This subsection provides a set of functions allowing to control the SDIO data
  260. transfers.
  261. @endverbatim
  262. * @{
  263. */
  264. /**
  265. * @brief Set SDIO Power state to ON.
  266. * @param SDIOx: Pointer to SDIO register base
  267. * @retval HAL status
  268. */
  269. HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx)
  270. {
  271. /* Set power state to ON */
  272. SDIOx->POWER = SDIO_POWER_PWRCTRL;
  273. return HAL_OK;
  274. }
  275. /**
  276. * @brief Set SDIO Power state to OFF.
  277. * @param SDIOx: Pointer to SDIO register base
  278. * @retval HAL status
  279. */
  280. HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)
  281. {
  282. /* Set power state to OFF */
  283. SDIOx->POWER = (uint32_t)0x00000000;
  284. return HAL_OK;
  285. }
  286. /**
  287. * @brief Get SDIO Power state.
  288. * @param SDIOx: Pointer to SDIO register base
  289. * @retval Power status of the controller. The returned value can be one of the
  290. * following values:
  291. * - 0x00: Power OFF
  292. * - 0x02: Power UP
  293. * - 0x03: Power ON
  294. */
  295. uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx)
  296. {
  297. return (SDIOx->POWER & SDIO_POWER_PWRCTRL);
  298. }
  299. /**
  300. * @brief Configure the SDIO command path according to the specified parameters in
  301. * SDIO_CmdInitTypeDef structure and send the command
  302. * @param SDIOx: Pointer to SDIO register base
  303. * @param SDIO_CmdInitStruct: pointer to a SDIO_CmdInitTypeDef structure that contains
  304. * the configuration information for the SDIO command
  305. * @retval HAL status
  306. */
  307. HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
  308. {
  309. uint32_t tmpreg = 0;
  310. /* Check the parameters */
  311. assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->CmdIndex));
  312. assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->Response));
  313. assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->WaitForInterrupt));
  314. assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->CPSM));
  315. /* Set the SDIO Argument value */
  316. SDIOx->ARG = SDIO_CmdInitStruct->Argument;
  317. /* Set SDIO command parameters */
  318. tmpreg |= (uint32_t)(SDIO_CmdInitStruct->CmdIndex |\
  319. SDIO_CmdInitStruct->Response |\
  320. SDIO_CmdInitStruct->WaitForInterrupt |\
  321. SDIO_CmdInitStruct->CPSM);
  322. /* Write to SDIO CMD register */
  323. MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg);
  324. return HAL_OK;
  325. }
  326. /**
  327. * @brief Return the command index of last command for which response received
  328. * @param SDIOx: Pointer to SDIO register base
  329. * @retval Command index of the last command response received
  330. */
  331. uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx)
  332. {
  333. return (uint8_t)(SDIOx->RESPCMD);
  334. }
  335. /**
  336. * @brief Return the response received from the card for the last command
  337. * @param SDIO_RESP: Specifies the SDIO response register.
  338. * This parameter can be one of the following values:
  339. * @arg SDIO_RESP1: Response Register 1
  340. * @arg SDIO_RESP2: Response Register 2
  341. * @arg SDIO_RESP3: Response Register 3
  342. * @arg SDIO_RESP4: Response Register 4
  343. * @retval The Corresponding response register value
  344. */
  345. uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
  346. {
  347. __IO uint32_t tmp = 0;
  348. /* Check the parameters */
  349. assert_param(IS_SDIO_RESP(SDIO_RESP));
  350. /* Get the response */
  351. tmp = SDIO_RESP_ADDR + SDIO_RESP;
  352. return (*(__IO uint32_t *) tmp);
  353. }
  354. /**
  355. * @brief Configure the SDIO data path according to the specified
  356. * parameters in the SDIO_DataInitTypeDef.
  357. * @param SDIOx: Pointer to SDIO register base
  358. * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure
  359. * that contains the configuration information for the SDIO command.
  360. * @retval HAL status
  361. */
  362. HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct)
  363. {
  364. uint32_t tmpreg = 0;
  365. /* Check the parameters */
  366. assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->DataLength));
  367. assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->DataBlockSize));
  368. assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->TransferDir));
  369. assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->TransferMode));
  370. assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->DPSM));
  371. /* Set the SDIO Data TimeOut value */
  372. SDIOx->DTIMER = SDIO_DataInitStruct->DataTimeOut;
  373. /* Set the SDIO DataLength value */
  374. SDIOx->DLEN = SDIO_DataInitStruct->DataLength;
  375. /* Set the SDIO data configuration parameters */
  376. tmpreg |= (uint32_t)(SDIO_DataInitStruct->DataBlockSize |\
  377. SDIO_DataInitStruct->TransferDir |\
  378. SDIO_DataInitStruct->TransferMode |\
  379. SDIO_DataInitStruct->DPSM);
  380. /* Write to SDIO DCTRL */
  381. MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
  382. return HAL_OK;
  383. }
  384. /**
  385. * @brief Returns number of remaining data bytes to be transferred.
  386. * @param SDIOx: Pointer to SDIO register base
  387. * @retval Number of remaining data bytes to be transferred
  388. */
  389. uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx)
  390. {
  391. return (SDIOx->DCOUNT);
  392. }
  393. /**
  394. * @brief Get the FIFO data
  395. * @param SDIOx: Pointer to SDIO register base
  396. * @retval Data received
  397. */
  398. uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx)
  399. {
  400. return (SDIOx->FIFO);
  401. }
  402. /**
  403. * @brief Sets one of the two options of inserting read wait interval.
  404. * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
  405. * This parameter can be:
  406. * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDIOCLK
  407. * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDIO_DATA2
  408. * @retval None
  409. */
  410. HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
  411. {
  412. /* Check the parameters */
  413. assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
  414. *(__IO uint32_t *)DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
  415. return HAL_OK;
  416. }
  417. /**
  418. * @}
  419. */
  420. /**
  421. * @}
  422. */
  423. #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
  424. #endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */
  425. /**
  426. * @}
  427. */
  428. /**
  429. * @}
  430. */
  431. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/